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ThinkMind // CENICS 2017, The Tenth International Conference on Advances in Circuits, Electronics and Micro-electronics // View article cenics_2017_2_30_60006


A Watt-Level 4G LTE CMOS Reconfigurable Power Amplifier with Efficiency Enhancement in Power Back-Off

Authors:
Giap Luong
Jean-Marie Pham
Pierre Medrel
Eric Kerhervé

Keywords: CMOS; Power Amplifier; transformer; segmented bias; differential; neutralization technique

Abstract:
This paper presents a reconfigurable two-stage power amplifier (PA) for use in 4G LTE unmanned aerial vehicles (UAVs) applications. The PA using the TSMC bulk 65-nm CMOS process exhibits a saturated output power of 29.8 dBm, a power gain of 35.6 dB, a maximum power added efficiency (PAE) of 27.2 % at 2.5 GHz and maintains PAE over 10 % in the output power’s 8 dB back-off zone as required by LTE’s power-to-average power ratio (PAPR) specifications. The proposed reconfigurable PA architecture, which includes four sub PA cells with the power cell switching (PCS) technique, allows the high level of efficiency in back-off of output power. The four sub-PA cells are composed of three differential cascode stages, supplied by 3.3 V and implemented with the segmented bias (SB) technique to maintain the high level of PAE, reduce the DC power consumption and reconfigure the output impedance

Pages: 28 to 32

Copyright: Copyright (c) IARIA, 2017

Publication date: September 10, 2017

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-585-2

Location: Rome, Italy

Dates: from September 10, 2017 to September 14, 2017

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