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ThinkMind // VALID 2012, The Fourth International Conference on Advances in System Testing and Validation Lifecycle // View article valid_2012_2_50_40051


Fault Detection Capabilities of an Enhanced Timing and Control Flow Checker for Hard Real-Time Systems

Authors:
Julian Wolf
Bernhard Fechner
Theo Ungerer

Keywords: Control flow checking; timing correctness; reliability; embedded processors; hard real-time computing

Abstract:
Dependability and robustness are essential requirements of embedded systems. It is necessary to develop and integrate mechanisms for a reliable fault detection. Regarding the context of hard real-time computing, such a mechanism should also focus on the correct timing behavior. In this paper, we present results of the fault detection capabilities, i.e., the fault coverage and detection latencies, of a novel timing and control flow checker designed for hard real-time systems. An experimental evaluation shows that more than 65% of injected faults uncaught by processor exceptions can be detected by our technique - at an average detection latency of only 22.1 processor cycles. Errors leading to endless loops can even be reduced by more than 90%, while the check mechanism causes only very low overhead concerning additional memory usage (15.0% on average) and execution time (12.2% on average).

Pages: 57 to 62

Copyright: Copyright (c) IARIA, 2012

Publication date: November 18, 2012

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-233-2

Location: Lisbon, Portugal

Dates: from November 18, 2012 to November 23, 2012

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