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ThinkMind // International Journal On Advances in Systems and Measurements, volume 10, numbers 1 and 2, 2017 // View article sysmea_v10_n12_2017_5


Improving FPGA-Placement with a Self-Organizing Map Accelerated by GPU-Computing

Authors:
Timm Bostelmann
Philipp Kewisch
Lennart Bublies
Sergei Sawitzki

Keywords: FPGA; netlist placement; OpenCL; GPU-computing; parallelization; SIMD

Abstract:
Programmable circuits and nowadays especially field-programmable gate arrays (FPGAs) are widely applied in computationally demanding signal processing applications. Considering modern, agile hardware / software codesign approaches, an electronic design automation (EDA) process not only needs to deliver high quality results. It also has to be swift because software compilation is already distinctly faster. Slow EDA tools can in fact act as a kind of show-stopper for an agile development process. One of the mayor problems in EDA is the placement of the technology-mapped netlist to the target architecture. In this work a method to improve the results of the netlist placement for FPGAs with a self-organizing map is presented. The admittedly high computational effort of this approach is covered by the exploitation of its inherent parallelism. Different approaches of parallelization are introduced and evaluated. A concept to accelerate the self-organizing map by using the single instruction multiple data (SIMD) capabilities of the central processing unit (CPU) and the graphics processing unit (GPU) for low-level vector operations is presented. This work is based on our previous publications, which are joined, updated and extend. Specifically, a new metric to generate training vectors for the self-organizing map -- that has been introduced by Amagasaki et al. -- was integrated into our work. It is shown that -- in case of our application -- the original vectorization metric creates higher quality results, even though the new metric is unmistakably faster. Addressing this issue, in addition to the previous low-level parallelization, a new high-level parallelization approach is introduced and detailed benchmark results are presented.

Pages: 45 to 55

Copyright: Copyright (c) to authors, 2017. Used with permission.

Publication date: June 30, 2017

Published in: journal

ISSN: 1942-261x

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