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ThinkMind // ICSNC 2012, The Seventh International Conference on Systems and Networks Communications // View article icsnc_2012_8_40_20178


Real Time FPGA Based Testbed for OFDM Development With ML Synchronization

Authors:
Tiago Pereira
Manuel Violas
Atílio Gameiro
Carlos Ribeiro
João Lourenço

Keywords: OFDM; FPGA; Software Defined Radio (SDR); physical layer; time-domain synchronization

Abstract:
In this paper, we present a real-time testbed Orthogonal Frequency Division Multiplexing (OFDM) signaling scheme. The testbed is implemented in a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. Time-domain synchronization is achieved through a joint maximum likelihood (ML) symbol- time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). Results show that a rough implementation of the signal path can be implemented by using only Xilinx System Generator for DSP. This work presents a valid FPGA implementation of an OFDM receiver synchronization algorithm using a high-level design tool.

Pages: 197 to 200

Copyright: Copyright (c) IARIA, 2012

Publication date: November 18, 2012

Published in: conference

ISSN: 2163-9027

ISBN: 978-1-61208-231-8

Location: Lisbon, Portugal

Dates: from November 18, 2012 to November 23, 2012

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